1. Field of the Invention
This invention is generally related to frequency synthesizers. More particularly, the invention relates to providing predictable oscillator sensitivity and/or substantially constant loop bandwidth in phase-locked loops.
2. Related Art
Frequency synthesizers are regularly employed in communication transceivers used in numerous types of communication systems and technologies. The frequency synthesizer typically includes a phase-locked loop (PLL) comprising an oscillator such as a voltage-controlled oscillator (VCO), a low-pass filter, and a phase and/or frequency detector. The phase and/or frequency detector controls the frequency of the output signal of the VCO. A phase and/or frequency detector in the PLL receives the output signal and compares the output signal to a reference frequency. Based on the comparison of the output signal to the reference frequency, the phase and/or frequency detector generates a control signal that is provided to the low-pass filter and then to the VCO. The control signal is typically received by a variable capacitor, sometimes referred to as a varactor, in the VCO. The control signal tunes the variable capacitor, thereby changing the frequency of the output signal of the VCO.
Wide-tuning VCO's can exhibit a sensitivity that is voltage and/or frequency dependent. Kv is a measure of the sensitivity of a VCO, and can be described algebraically as follows:
                              K          V                =                              ∂                          f              VCO                                            ∂                          V              control                                                          (                  Eq          .                                          ⁢          1                )            where fVCO is the VCO output frequency and Vcontrol is the VCO control voltage. PLLs often use off-chip components for the loop filter. With the industry moving towards higher integration/systems on a chip, integrating the loop filter is one of the primary challenges to implementing systems on a chip. In PLLs that require fast settling times, a frequency dependent Kv can make loop filter design a difficult task, especially when integrating the filter on a semiconductor chip.
In addition, for wide-band oscillators, there is a large variation in loop bandwidth, and PLL settling times and noise performance can severely deteriorate.
Therefore it would be desirable to provide a PLL with a constant or substantially constant bandwidth and/or a predictable Kv.